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1 features ? ultra high performance C system speeds to 100 mhz C array multipliers > 50 mhz C 10ns flexible sram C internal 3-state capability in each cell ? freeram ? C flexible, single/dual port, sync/async 10 ns sram C 2,048 - 18,432 bits of distributed sram independent of logic cells ? 84 - 384 pci compliant i/os C 3v/5v capability C programmable output drive C fast, flexible array access facilitates pin-locking C pin compatible with xc4000, xc5200 fpgas ? 8 global clocks C fast, low skew clock distribution C programmable rising/falling edge transitions C distributed clock shut-down capability for low power management C global reset/asynchronous reset options C 4 additional dedicated pci clocks ? cache logic ? dynamic full/partial reconfigurability in-system C unlimited reprogrammability via serial or parallel modes C enables adaptive designs C enables fast vector multiplier updates C quickchange ? tools for fast, easy design changes ? pin-compatible package options C plastic leaded chip carriers (plcc) C thin, plastic quad flat packs (vqfp, tqfp, pqfp) C ball grid arrays (bga) C pin grid arrays (pgas) ? industry-standard design tools C seamless integration (libraries, interface, full back-annotation) with concept, everest, exemplar, mentor, orcad, synario, synopsys, verilog, veribest, viewlogic, synplicity C timing driven placement & routing C automatic/interactive multi-chip partitioning C fast, efficient synthesis C over 50 automatic component generators create 1000s of reusable, fully deterministic logic and ram functions ? intellectual property cores C fir filters, uarts, pci, fft and other system level functions ? easy migration to atmel gate arrays for high volume production device at40k05 at40k10 at40k20 at40k40 usable gates 5k - 10k 10k - 20k 20k - 30k 40k - 50k rowsxcolumns 16 x 16 24 x 24 32 x 32 48 x 48 cells 256 576 1,024 2,304 registers 256 576 1,024 2,304 ram bits 2,048 4,608 8,192 18,432 i/o (max) 128 192 256 384 at40k fpgas with freeram? at40k05 at40k10 at40k20 at40k40 rev. 0896bC01/99 at40k
at40k 2 description the at40k is a family of fully pci-compliant, sram-based fpgas with distributed 10ns programmable synchro- nous/asynchronous, dual port/single port sram, 8 global clocks, cache logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. i/o counts range from 128 to 384 in industry standard packages rang- ing from 84-pin plcc to 475-pin bga, and support 3.3v and 5v designs. the at40k is designed to quickly implement high perfor- mance, large gate count designs through the use of synthe- sis and schematic-based tools used on a pc, sun and hp platform. atmels design tools provide seamless integration with industry standard tools from cadence (concept/ver- ilog), everest, exemplar, mentor, orcad, synario, veri- best, and viewlogic. the at40k can be used as a coprocessor for high speed (dsp/processor-based) designs by implementing a variety of compute-intensive, arithmetic functions. these include adaptive finite impulse response (fir) filters, fast fourier transforms (fft), convolvers, interpolators and discrete- cosine transforms (dct) that are required for video com- pression and decompression, encryption, convolution and other multimedia applications . fast, flexible and efficient sram the at40k fpga offers a patented distributed 10ns sram capability where the ram can be used without los- ing logic resources. multiple independent, synchronous or asynchronous, dual port or single port ram functions (fifo, scratch pad, etc.) can be created using atmels macro generator tool. fast, efficient array & vector multipliers the at40ks patented 8-sided core cell with direct horizon- tal, vertical and diagonal cell-to-cell connections imple- ments ultra fast array multipliers without using any busing resources. the at40ks cache logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional fpgas. cache logic design the at40k is the only fpga family capable of implement- ing cache logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. as new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. the at40k can act as a reconfigurable coprocessor. automatic component generators the at40k is the only fpga family capable of implement- ing user-defined, automatically generated, macros in multi- ple designs; speed and functionality are unaffected by the macro orientation or density of the target device. this enables the fastest, most predictable and efficient fpga design approach and minimizes design risk by reusing already proven functions. the automatic component gen- erators work seamlessly with industry standard schematic and synthesis tools to create the fastest, most efficient designs available. the patent-pending at40k series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. independently controlled clocks and resets govern every column of cells. the array is sur- rounded by programmable i/o. devices range in size from 5,000 to 50,000 usable gates in the initial family, and 256 to 2,304 registers. pin locations are consistent throughout the at40k series for easy design migration in the same package footprint. at40k series fpgas utilize a reliable 0.6 micron single-poly, tri- ple-metal cmos process and are 100% factory-tested. atmels pc- and workstation-based integrated develop- ment system is used to create at40k series designs. mul- tiple design entry methods are supported. the atmel architecture was developed to provide the high- est levels of performance, functional density and design flexibility in an fpga. the cells in the atmel array are small, efficient and can implement any pair of boolean functions of (the same) three inputs or any single boolean function of four inputs. the cells small size leads to arrays with large numbers of cells, greatly multiplying the function- ality in each cell. a simple, high-speed busing network pro- vides fast, efficient communication over medium and long distances
at40k 3 the symmetrical array at the heart of the atmel architecture is a symmetrical array of identical cells (figure 1). the array is continuous from one edge to the other, except for bus repeaters spaced every four cells (figure 2). at the intersection of each repeater row and column is a 32 x 4 ram block accessible by adjacent buses. the ram can be configured as either a single-ported or dual-ported ram, with either synchronous or asynchronous operation. figure 1. symmetrical array surrounded by i/o (at40k20) = i/o pad = at40k cell = repeater row = repeater column
at40k 4 figure 2. floorplan (representative portion) the busing network figure 3 depicts one of five identical busing planes. each plane has 3 bus resources: a local-bus resource (the mid- dle bus) and 2 express-bus resources. bus resources are connected via repeaters. each repeater has connections to two adjacent local-bus segments and two express-bus seg- ments. each local-bus segment spans four cells and con- nects to consecutive repeaters. each express-bus segment spans eight cells and leapfrogs or bypasses a repeater. repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip three state buses to be created. local/local turns are imple- mented through pass gates in the cell-bus interface (see following page). express/express turns are implemented through separate pass gates distributed throughout the array. rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rh = vertical repeater = horizontal repeater = cell ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram
at40k 5 figure 3. busing plane (one of five) = local/local or express/express turn point = at40k cell = row repeater = column repeater
at40k 6 cell connections figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. figure 4(b) shows the connec- tions between a cell five horizontal local buses (one per busing plane) and five vertical local buses (one per busing plane). figure 4. cell connections cel cel cel cel cel cel cel cel cel cel (a) cell to cell connections (b) cell to bus connections w x y z l wxyzl
at40k 7 the cell figure 5 depicts the at40k cell. configuration bits for sep- arate muxes and pass gates are independent. all permuta- tions of programmable muxes and pass gates are legal. vn is connected to the vertical local bus in plane n. hn is con- nected to the horizontal local bus in plane n. a local/local turn in plane n is achieved by turning on the two pass gates connected to vn and hn. up to five simultaneous local/local turns are possible. figure 5. the cell the core cell can be configured in several modes. the core cell flexibility makes the at40k architecture well suited to most digital design application areas (see figure 6). out out reset/set clock fb x = diagonal direct connect or bus y = orthogonal direct connect or bus w = bus connection z = bus connection fb = internal feedback 10 z d q "1" nw ne se sw "1" "1" "1" "0" xwy x zwy "1" n e s w 8x1 lut 8x1 lut x y nw ne se sw n e s w v1 h1 v2 h2 v3 h3 v4 h4 v5 h5 "1" oe h oe v l
at40k 8 figure 6. some single cell modes lut lut lut lut lut 2:1 mux lut lut dq dq q q (registered) dq dq synthesis mode arithmetic mode dsp/multiplier mode counter mode tri-state / mux mode a b c d a b c a b c d a b c en q q sum (registered) sum and/or product or carry product (registered) carry carry carry in and/or or and/or and/or
at40k 9 ram 32 x 4 dual-ported ram blocks are dispersed throughout the array as shown in figure 7. a four-bit input data bus connects to four horizontal local buses distributed over four sector rows (plane 1). a four-bit output data bus connects to four horizontal local buses distributed over four sector rows (plane 2). a five-bit input-address bus connects to five vertical express buses in same column. a five-bit out- put-address bus connects to five vertical express buses in same column. waddr (write address) and raddr (read address) alternate positions in horizontally aligned ram blocks. for the left-most ram blocks, raddr is on the left and waddr is on the right. for the right-most ram blocks, waddr is on the left and raddr is tied off. for single-ported ram, waddr is the read/write address port and din is the (bi-directional) data port. right-most ram blocks can be used only for single-ported memories. /we & /oe con- nect to the vertical express buses in the same column. waddr, raddr, /we and /oe connect to express buses that are full length at array edge. figure 7. ram connections (one ram block) 32x4 di wadd w o dou radd cl cl cl cl cl
at40k 10 reading and writing the 32 x 4 dual-port ram are inde- pendent of each other. reading the 32 x 4 dual-port ram is completely asynchronous. latches are transparent; when load is logic 1, data flows through; when load is logic 0, data is latched. each bit in the 32 x 4 dual-port ram is also a transparent latch. the front-end latch and the memory latch together form an edge-triggered flip flop. when a bit = 7 nibble is (write) addressed and load is logic 1 and we is logic 0, data flows through the bit. when a nibble is not (write) addressed or load is logic 0 or we is logic 1, data is latched in the nibble. the two clock muxes are controlled together; they both select clock or they both select 1. clock is obtained from the clock for the sector-column immediately to the left and immediately above the ram block. writing any value to the ram clear byte during configuration clears the ram (see bit map spec). figure 8. ram logic write data data read "1 "1 write enable ram-clear data out "1 clock load 5 read addr write addr we data i n load latch load latch load latch clear 32 x 4 dual-port ram oe 4 4 5
at40k 11 figure 9. ram example: 128 x 8 dual-ported ram (asynchronous) 2-to-4 decoder dout(4) dout(5) dout(6) dout(7) din dout we oe raddr waddr din dout din dout we oe din dout waddr raddr we oe raddr waddr we oe waddr raddr din dout waddr raddr we oe din dout we oe raddr waddr din dout waddr raddr we oe din dout we oe raddr waddr 2-to-4 decoder local buses express buses dedicated connections read address din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) write address we dout(0) dout(1) dout(2) dout(3)
at40k 12 clocking and set/reset each of 8 dedicated global clock buses is connected to a dual-use global clock pad (gck1 - gck8). an internal sig- nal can be placed on a global clock bus by routing that sig- nal to a global clock pad. each column of the array has a column clock selected from one of the 8 global clock buses. the extreme-left column clock mux has two addi- tional inputs from dual-use pins fck1 & fck2 to provide fast clocking to left-side i/o. the extreme-right column clock mux has two additional inputs from dual-use pins fck3 & fck4 to provide fast clocking to right-side i/o. each sector column of 4 cells can be clocked from a (plane 4) express bus or from the column clock. clocking to the 4 cells can be disabled. the plane 4 express bus used for clocking is half length at the array edge. the clock provided to each sector column of 4 cells can be either inverted or not inverted. the register in each cell is triggered on a ris- ing clock edge. on power up, constant 0 is provided to each registers clock pins. a dedicated global set/reset bus can be driven by any user i/o pad, except those used for clocking, global or fast. an internal signal can be placed on the global set/reset bus by routing that signal to the pad pro- grammed as the global set/reset input. global set/reset is distributed to each column of the array. each sector col- umn of 4 cells can be set/reset by a (plane 5) express bus or by the global set/reset. the plane 5 express bus used for set/reset is half length at array edge. the set/reset provided to each sector column of 4 cells can be either inverted or not inverted. the function of the set/reset input of a register (either set or reset) is determined by a config- uration bit in each cell. the set/reset input of a register is active low (logic 0). setting or resetting of a register is asynchronous. on power up, a logic 1 (a high) is provided by each register, i.e., all registers are set at power up.
at40k 13 figure 10. clocking (for one column of cells) global clock line (buried) express bus (plane 4; half length at edge) gck1 - gck8 repeater } fck (2 per edge column of cells) } "1" "1" "1" "1"
at40k 14 figure 11. set/reset (for one column of cells) each cell has a programmable set or reset global set/reset line (buried) repeater express bus (plane 5; half length at edge) any user i/o can drive global set/reset line "1" "1" "1" "1"
at40k 15 figure 12. west i/o (mirrored for east i /o) (a) primary (a) secondary pa cel cel cel ttl/cmos drive pull- vcc tri-state pull-down gnd delay schmitt "0 "1 "0 "1 pa cel cel pull- vcc pull-down gnd drive tri-state ttl/cmos delay schmitt "0 "1 "1 "0
at40k 16 figure 13. south i/o (mirrored for north i/o) vc ttl/cmo gn pull-up pa driv tri- pull-down dela schmit "0" "1" "0" "1" cel cel cel pa gn pull-up pull-down ttl/cmo driv vc tri- dela schmit "0" "1" "1" "0" cel cel (a) primary (a) secondary
at40k 17 figure 14. north/west corner, (similar for ne/se/sw corners) cel gn pull-up pull-down ttl/cmo driv vc tri- dela schmit pa ttl/cmo driv pull-up vc tri- pull-down gn dela schmit pa pa cel ttl/cmos drive pull- vcc tri-state pull-down gnd delay schmitt "0 "1 "0 "1 "0" "1" "0" "1" "0" "1" "0" "1" cel
at40k 18 some of the bus resource on atk40k is used as a dual- function resource. table 1 shows which buses are used in a dual-function mode and which bus plane is used. the atk40k software tools are designed to accommodate dual-function buses in an efficient manner. table 1. dual-function buses function type plane(s) direction comments cell output enable local 5 horizontal and ver tical ram output enable express 2 vertical bus full length at array edge bus in first column to left of ram block ram write enable express 1 vertical bus full length at array edge bus in first column to left of ram block ram address express 1-5 vertical buses full length at array edge buses in second column to left of ram block ram data in local 1 horizontal ram data out local 2 horizontal clocking express 4 vertical bus half length at array edge set/reset express 5 vertical bus half length at array edge
at40k 19 note: 1. minimum voltage of -0.5v dc which may undershoot to -2.0v for pulses of less than 20 ns. *notice: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper- ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings - 5v commercial/industrial* symbol parameter conditions min max units v cc supply voltage with respect to gnd -0.5 7.0 v v i dc input voltage (1) with respect ot gnd -0.5 7.0 v v o dc output voltaage with respect ot gnd -0.5 7.0 v t stg storage temperature -65 c+150 c t j junction temperature +150 c t l lead temperature (soldering, 10 sec.) +250 c esd r zap = 1.5k, c zap = 100 pf 2000 v dc and ac operating range - 5v operation at40k05-2 at40k10-2 at40k20-2 at40k40-2 commercial at40k05-2 at40k10-2 at40k20-2 at40k40-2 industrial at40k05-2 at40k10-2 at40k20-2 at40k40-2 military operating temperature (case) 0 c - 70 c -40 c - 85 c -55 c - 125 c v cc power supply 5v 5% 5v 10% 5v 10% input voltage level (ttl) high (v iht ) 2.0v - v cc 2.0v - v cc 2.0v - v cc low (v ilt ) 0v - 0.8v 0v - 0.8v 0v - 0.8v input voltage level (cmos) high (v ihc ) 70% - 100% v cc 70% - 100% v cc 70% - 100% v cc low (v ilc ) 0 - 30% v cc 0 - 30% v cc 0 - 30% v cc
at40k 20 dc characteristics - 5v operation - commercial/industrial/military symbol parameter conditions min typ max units v ih high-level input voltage cmos 70% v cc v ttl 2.0 v v il low-level input voltage cmos -0.3 30% v cc v ttl -0.3 0.8 v v oh high-level output voltage i oh = 6ma v cc = v cc min 4.0 v i oh = 14ma v cc = v cc min 4.0 v i oh = 20ma comm. = 4.75v ind./military = 4.5v 4.0 v v ol low-level output voltage i ol = -6ma comm. = 4.75v ind./military = 4.5v 0.4 v i ol = -14ma comm. = 4.75v ind./military = 4.5v 0.4 v i ol = -20ma comm. = 4.75v ind./military = 4.5v 0.4 v i ih high-level input current v in = v cc max 10 a with pulldown, v in = v cc 125 250 500 a i il low-level input current v in = v ss -10 a with pullup, v in = v ss -500 -250 -125 a i ozh high-level tristate output leakage current without pulldown, v in = v cc 10 a with pulldown, v in = v cc 125 250 500 a i ozl low-level tristate output leakage current without pullup, v in = v ss max -10 a with pullup, v in = v ss max -500 -250 -125 a i cc standby current consumption standby, unprogrammed 0.6 1 ma c in input capacitance all pins 10 pf
at40k 21 ac timing characteristics - 5v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 4.75v, temperature = 70 c minimum times based on best case: v cc = 5.25v, temperature = 0 c maximum delays are the average of t pdlh and t pdhl . cell function parameter path -2 units notes core 2 input gate t pd (max) x/y -> x/y 1.8 ns 1 unit load 3 input gate t pd (max) x/y/z -> x/y 2.1 ns 1 unit load 3 input gate t pd (max) x/y/w -> x/y 2.2 ns 1 unit load 4 input gate t pd (max) x/y/w/z -> x/y 2.2 ns 1 unit load fast carry t pd (max) y -> y 1.4 ns 1 unit load fast carry t pd (max) x -> y 1.7 ns 1 unit load fast carry t pd (max) y -> x 1.8 ns 1 unit load fast carry t pd (max) x -> x 1.5 ns 1 unit load fast carry t pd (max) w -> y 2.2 ns 1 unit load fast carry t pd (max) w -> x 2.3 ns 1 unit load fast carry t pd (max) z -> y 2.3 ns 1 unit load fast carry t pd (max) z -> x 1.7 ns 1 unit load dff t pd (max) q -> x/y 1.8 ns 1 unit load dff t setup (min) x/y -> clk ns dff t hold (min) x/y -> clk ns dff t pd (max) r -> x/y 2.2 ns 1 unit load dff t pd (max) s -> x/y 2.2 ns 1 unit load dff t pd (max) q -> w 1.8 ns incremental --> l t pd (max) x/y -> l 1.5 ns 1 unit load local output enable t pzx (max) oe -> l 1.4 ns 1 unit load local output enable t pxz (max) oe -> l 1.8 ns
at40k 22 all input io characteristics measured from a v ih of 50% at the pad (cmos threshold) to the internal v ih of 50% of v cc . all output io characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v cc . ac timing characteristics - 5v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 4.75v, temperature = 70 c minimum times based on best case: v cc = 5.25v, temperature = 0 c max delays are the average of t pdlh and t pdhl . all input io characteristics measured from a v ih of 50% of v dd at the pad (cmos threshold) to the internal v ih of 50% of v c . all output io characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v cc . cell function parameter path -2 units notes repeaters repeater t pd (max) l->e 1.3 ns 1 unit load repeater t pd (max) e->e 1.3 ns 1 unit load repeater t pd (max) l->l 1.3 ns 1 unit load repeater t pd (max) e->l 1.3 ns 1 unit load repeater t pd (max) e->io 0.8 ns 1 unit load repeater t pd (max) l->io 0.8 ns 1 unit load cell function parameter path -2 units notes io input t pd (max) pad -> x/y 1.2 ns no extra delay input t pd (max) pad -> x/y 3.6 ns 1 extra delay input t pd (max) pad -> x/y 7.3 ns 2 extra delays input t pd (max) pad -> x/y 10.8 ns 3 extra delays output, slow t pd (max) x/y/e/l -> pad 5.9 ns 50pf load output, medium t pd (max) x/y/e/l -> pad 4.8 ns 50pf load output, fast t pd (max) x/y/e/l -> pad 3.9 ns 50pf load output, slow t pzx (max) oe -> pad 6.2 ns 50pf load output, low t pxz (max) oe -> pad 1.3 ns 50pf load output, medium t pzx (max) oe -> pad 4.8 ns 50pf load output, medium t pxz (max) oe -> pad 1.9 ns 50pf load output, fast t pzx (max) oe -> pad 3.7 ns 50pf load output, fast t pxz (max) oe -> pad 1.6 ns 50pf load
at40k 23 ac timing characteristics - 5v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 4.75v, temperature = 70 c minimum times based on best case: v cc = 5.25v, temperature = 0 c max delays are the average of t pdlh and t pdhl . clocks and reset input buffers are measured from a v ih of 1.5v at the input pad to the internal v ih of 50% of v cc . maximum times for clock input buffers and internal drivers are measured for rising edge delays only. cell function parameter path device -2 units notes global clocks and set/reset gclk input buffer t pd (max) pad -> clock pad -> clock pad -> clock pad -> clock at40k05 at40k10 at40k20 at40k40 1.1 1.2 1.2 1.4 ns ns ns ns rising edge clock fclk input buffer t pd (max) pad -> clock pad -> clock pad -> clock pad -> clock at40k05 at40k10 at40k20 at40k40 0.7 0.8 0.8 0.8 ns ns ns ns rising edge clock clock column driver t pd (max) clock -> colclk clock -> colclk clock -> colclk clock -> colclk at40k05 at40k10 at40k20 at40k40 0.8 0.9 1.0 1.1 ns ns ns ns rising edge clock clock sector driver t pd (max) colclk -> secclk colclk -> secclk colclk -> secclk colclk -> secclk at40k05 at40k10 at40k20 at40k40 0.5 0.5 0.5 0.5 ns ns ns ns rising edge clock gsrn input buffer t pd (max) pad -> gsrn colclk -> secclk colclk -> secclk colclk -> secclk at40k05 at40k10 at40k20 at40k40 3.0 3.7 4.3 5.6 ns ns ns ns global clock to output t pd (max) clock pad -> out clock pad -> out clock pad -> out clock pad -> out at40k05 at40k10 at40k20 at40k40 8.3 8.4 8.6 8.8 ns ns ns ns rising edge clock fully loaded clock tree rising edge dff 20ma output buffer 50 pf pin load output, fast t pd (max) clock pad -> out clock pad -> out clock pad -> out clock pad -> out at40k05 at40k10 at40k20 at40k40 7.9 8.0 8.1 8.3 ns ns ns ns rising edge clock fully loaded clock tree rising edge dff 20ma output buffer 50 pf pin load
at40k 24 ac timing characteristics - 5v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 4.75v, temperature = 70 c minimum times based on best case: v cc = 5.25v, temperature = 0 c max delays are the average of t pdlh and t pdhl . cell function parameter path -2 units notes async ram write t wecyc (min) cycle time 8.0 ns write t wel (min) we 3.0 ns pulse width low write t weh (min) we 3.0 ns pulse width high write t setup (min) wr addr setup-> we 2.0 ns write t hold (min) wr addr hold -> we 0.0 ns write t setup (min) din setup -> we 2.0 ns write t hold (min) din hold -> we 0.0 ns write t hold (min) oe hold -> we 0.0 ns write/read t pd (max) din -> dout 4.6 ns rd addr = wr addr read t pd (max) rd addr -> dout 3.1 ns read t pzx (max) oe -> dout 1.6 ns read t pxz (max) oe -> dout 2.0 ns sync ram write t cyc (min) cycle time 8.0 ns write t clkl (min) clk 3.0 ns pulse width low write t clkh (min) clk 3.0 ns pulse width high write t setup (min) we setup-> clk 2.0 ns write t hold (min) we hold -> clk 0.0 ns write t setup (min) wr addr setup-> clk 2.0 ns write t hold (min) wr addr hold -> clk 0.0 ns write t setup (min) wr data setup-> clk 2.0 ns write t hold (min) wr data hold -> clk 0.0 ns write/read t pd (max) din -> dout 4.6 ns rd addr = wr addr write/read t pd (max) clk -> dout 3.5 ns rd addr = wr addr read t pd (max) rd addr -> dout 3.1 ns read t pzx (max) oe -> dout 1.6 ns read t pxz (max) oe -> dout 2.0 ns
at40k 25 note: 1. minimum voltage of -0.5v dc which may undershoot to -2.0v for pulses of less than 20 ns. *notice: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper- ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings - 3.3v commercial/industrial* symbol parameter conditions min max units v cc supply voltage with respect to gnd -0.5 7.0 v v i dc input voltage (1) with respect ot gnd -0.5 7.0 v v o dc output voltaage with respect ot gnd -0.5 7.0 v t stg storage temperature -65 c+150 c t j junction temperature +150 c t l lead temperature (soldering, 10 sec.) +250 c esd r zap = 1.5k, c zap = 100 pf 2000 v dc and ac operating range - 3.3v operation at40k05lv-4/3/2 at40k10lv-4/3/2 at40k20lv-4/3/2 at40k40lv-4/3/2 commercial at40k05lv-4/3/2 at40k10lv-4/3/2 at40k20lv-4/3/2 at40k40lv-4/3/2 industrial operating temperature (case) 0 c - 70 c-40 c - 85 c v cc power supply 3.3v 0.3v 3.3v 0.3v input voltage level (cmos) high (v ihc ) 70% - 100% v cc 70% - 100% v cc low (v ilc ) 0 - 30% v cc 0 - 30% v cc
at40k 26 note: 1. parameter based on characterization and simulation; it is not tested in production. dc characteristics - 3.3v operation - commercial/industrial symbol parameter conditions min typ max units v ih high-level input voltage cmos 70% v cc v ttl 2.0 v v il low-level input voltage cmos -0.3 30% v cc v ttl -0.3 0.8 v v oh high-level output voltage i oh = 4 ma v cc = v cc min 2.1 v i oh = 12 ma v cc = 3.0v 2.1 v i oh = 16 ma v cc = 3.0v 2.1 v v ol low-level output voltage i ol = -4 ma v cc = 3.0v 0.4 v i ol = -12 ma v cc = 3.0v 0.4 v i ol = -16 ma v cc = 3.0v 0.4 v i ih high-level input current v in = v cc max 10 a with pulldown, v in = v cc 75 150 300 a i il low-level input current v in = v ss -10 a with pullup, v in = v ss -300 -150 -75 a i ozh high-level tristate output leakage current without pulldown, v in = v cc max 10 a with pulldown, v in = v cc max 75 150 300 a i ozl low-level tristate output leakage current without pullup, v in = v ss -10 m a with pullup, v in = v ss -300 -150 -75 a i cc standby current consumption standby, unprogrammed 0.6 1 ma c in input capacitance all pins 10 pf
at40k 27 ac timing characteristics - 3.3v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.00v, temperature = 70 c minimum times based on best case: v cc = 3.60v, temperature = 0 c max delays are the average of t pdlh and t pdhl . cell function parameter path -3 units notes core 2 input gate t pd (max) x/y -> x/y 2.9 ns 1 unit load 3 input gate t pd (max) x/y/z -> x/y 2.8 ns 1 unit load 3 input gate t pd (max) x/y/w -> x/y 3.4 ns 1 unit load 4 input gate t pd (max) x/y/w/z -> x/y 3.4 ns 1 unit load fast carry t pd (max) y -> y 2.3 ns 1 unit load fast carry t pd (max) x -> y 2.9 ns 1 unit load fast carry t pd (max) y -> x 3.0 ns 1 unit load fast carry t pd (max) x -> x 2.3 ns 1 unit load fast carry t pd (max) w -> y 3.4 ns 1 unit load fast carry t pd (max) w -> x 3.4 ns 1 unit load fast carry t pd (max) z -> y 3.4 ns 1 unit load fast carry t pd (max) z -> x 2.4 ns 1 unit load dff t pd (max) q -> x/y 2.8 ns 1 unit load dff t setup (min) x/y -> clk ns dff t hold (min) x/y -> clk ns dff t pd (max) r -> x/y 3.2 ns 1 unit load dff t pd (max) s -> x/y 3.0 ns 1 unit load dff t pd (max) q -> w 2.7 ns incremental --> l t pd (max) x/y -> l 2.4 ns 1 unit load local output enable t pzx (max) oe -> l 2.8 ns 1 unit load local output enable t pxz (max) oe -> l 2.4 ns
at40k 28 ac timing characteristics - 3.3v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.0v, temperature = 70 c minimum times based on best case: v cc = 3.6v, temperature = 0 c max delays are the average of t pdlh and t pdhl . all input io characteristics measured from a v ih of 50% of v dd at the pad (cmos threshold) to the internal v ih of 50% of v dd . all output io characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v dd . cell function parameter path -3 units notes repeaters repeater t pd (max) l -> e 2.2 ns 1 unit load repeater t pd (max) e -> e 2.2 ns 1 unit load repeater t pd (max) l -> l 2.2 ns 1 unit load repeater t pd (max) e -> l 2.2 ns 1 unit load repeater t pd (max) e -> io 1.4 ns 1 unit load repeater t pd (max) l -> io 1.4 ns 1 unit load all input io characteristics measured from a v ih of 50% of v dd at the pad (cmos threshold) to the internal v ih of 50% of v dd . all output io characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v dd . cell function parameter path -3 units notes io input t pd (max) pad -> x/y 1.9 ns no extra delay input t pd (max) pad -> x/y 5.8 ns 1 extra delay input t pd (max) pad -> x/y 11.5 ns 2 extra delays input t pd (max) pad -> x/y 17.4 ns 3 extra delays output, slow t pd (max) x/y/e/l -> pad 9.1 ns 50pf load output, medium t pd (max) x/y/e/l -> pad 7.6 ns 50pf load output, fast t pd (max) x/y/e/l -> pad 6.2 ns 50pf load output, slow t pzx (max) oe -> pad 9.5 ns 50pf load output, slow t pxz (max) oe -> pad 2.1 ns 50pf load output, medium t pzx (max) oe -> pad 7.4 ns 50pf load output, medium t pxz (max) oe -> pad 2.7 ns 50pf load output, fast t pzx (max) oe -> pad 5.9 ns 50pf load output, fast t pxz (max) oe -> pad 2.4 ns 50pf load
at40k 29 ac timing characteristics - 3.3v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.0v, temperature = 70 c minimum times based on best case: v cc = 3.6v, temperature = 0 c max delays are the average of t pdlh and t pdhl . clocks and reset input buffers are measured from a vih of 1.5v at the input pad to the internal vih of 50% of vcc. maximum times for clock input buffers and internal drivers are measured for rising edge delays only. cell function parameter path device -3 units notes global clocks and set/reset gck input buffer t pd (max) pad -> clock pad -> clock pad -> clock pad -> clock at40k05 at40k10 at40k20 at40k40 1.3 1.5 1.6 1.9 ns ns ns ns rising edge clock fck input buffer t pd (max) pad -> clock pad -> clock pad -> clock pad -> clock at40k05 at40k10 at40k20 at40k40 0.7 0.8 0.8 0.9 ns ns ns ns rising edge clock clock column driver t pd (max) clock -> colclk clock -> colclk clock -> colclk clock -> colclk at40k05 at40k10 at40k20 at40k40 1.5 1.8 2.0 2.5 ns ns ns ns rising edge clock clock sector driver t pd (max) colclk -> secclk colclk -> secclk colclk -> secclk colclk -> secclk at40k05 at40k10 at40k20 at40k40 1.0 1.0 1.0 1.0 ns ns ns ns rising edge clock gsrn input buffer t pd (max) pad -> gsrn colclk -> secclk colclk -> secclk colclk -> secclk at40k05 at40k10 at40k20 at40k40 4.5 5.4 6.3 8.2 ns ns ns ns global clock to output t pd (max) clock pad -> out clock pad -> out clock pad -> out clock pad -> out at40k05 at40k10 at40k20 at40k40 13.0 13.4 13.8 14.5 ns ns ns ns rising edge clock fully loaded clock tree rising edge dff 20ma output buffer 50 pf pin load fast clock to output t pd (max) clock pad -> out clock pad -> out clock pad -> out clock pad -> out at40k05 at40k10 at40k20 at40k40 12.4 12.7 13.0 13.5 ns ns ns ns rising edge clock fully loaded clock tree rising edge dff 20ma output buffer 50 pf pin load
at40k 30 notes: 1. cmos buffer delays are measured from a v ih of 1/2 v cc at the pad to the internal v ih at a. the input buffer load is constant. 2. buffer delay is to a pad voltage of 1.5v with one output switching. 3. parameter based on characterization and simulation; not tested in production. 4. exact power calculation is available in atmel fpga designer software. ac timing characteristics - 3.3v operation delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.0v, temperature = 70 c minimum times based on best case: v cc = 3.6v, temperature = 0 c cell function parameter path -4 -3 units notes async ram write t wecyc (min) cycle time 14.0 12.0 ns write t wel (min) we 6.0 5.0 ns pulse width low write t weh (min) we 6.0 5.0 ns pulse width high write t setup (min) wr addr setup-> we 5.3 5.3 ns write t hold (min) wr addr hold -> we 0.0 0.0 ns write t setup (min) din setup -> we 6.0 5.0 ns write t hold (min) din hold -> we 0.0 0.0 ns write t hold (min) oe hold -> we 0.0 0.0 ns write/read t pd (max) din -> dout 12.1 8.7 ns rd addr = wr addr read t pd (max) rd addr -> dout 9.7 6.3 ns read t pzx (max) oe -> dout 4.2 2.9 ns read t pxz (max) oe -> dout 3.5 3.5 ns sync ram write t cyc (min) cycle time 12.0 12.0 ns write t clkl (min) clk 6.0 5.0 ns pulse width low write t clkh (min) clk 6.0 5.0 ns pulse width high write t setup (min) we setup-> clk 3.2 3.2 ns write t hold (min) we hold -> clk 0.0 0.0 ns write t setup (min) wr addr setup-> clk 6.0 5.0 ns write t hold (min) wr addr hold -> clk 0.0 0.0 ns write t setup (min) wr data setup-> clk 3.0 3.9 ns write t hold (min) wr data hold -> clk 0.0 0.0 ns write/read t pd (max) din -> dout 12.1 8.7 ns rd addr = wr addr write/read t pd (max) clk -> dout 9.9 5.8 ns rd addr = wr addr read t pd (max) rd addr -> dout 9.7 6.3 ns read t pzx (max) oe -> dout 4.01 2.9 ns read t pxz (max) oe -> dout 3.5 3.5 ns
at40k 31 devices in same packages are pin-for-pin replaceable. part/package availability at40k05 at40k10 at40k20 at40k40 pc 84 xxx rq100 x x vq 100 xxx tq 144 xxxx pq 160 xxx pq 208 xxxx pq 240 xxx pq 304 xx bg 225 xx bg 352 xx bg 432 x pg 475 x user i/o counts - (including dual-function pins) at40k05 at40k10 at40k20 at40k40 pc 84 62 62 62 rq 100 78 78 vq 100 787878 tq 144 114 114 114 114 pq 160 128 130 130 pq 208 128 161 161 161 pq 240 192 193 193 pq 304 256 256 bg 225 192 192 bg 352 256 289 bg 432 352 pg 475 384
at40k 32 at40k05 at40k10 at40k20 at40k40 left side (top to bottom) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 gnd gnd gnd gnd 12 4 1 1 1 2 gnd (1) 1304gnd (1) gnd (1) i/o1, gck1 (a16) i/o1, gck1 (a16) i/o1, gck1 (a16) i/o1, gck1 (a16) 135 2 2 2 4d42303d23d29 i/o2 (a17) i/o2 (a17) i/o2 (a17) i/o2 (a17) 146 3 3 3 5b13302c25c30 i/o3 i/o3 i/o3 i/o3 4 4 6 c2 4 301 d24 e28 i/o4 i/o4 i/o4 i/o4 5 5 7 e5 5 300 e23 e29 i/o5 (a18) i/o5 (a18) i/o5 (a18) i/o5 (a18) 157 4 6 6 8d36299c26d30 i/o6 (a19) i/o6 (a19) i/o6 (a19) i/o6 (a19) 168 5 7 7 9c17298e24d31 gnd gnd (1) i/o7 f28 i/o8 f29 i/o9 d25 e30 i/o10 f23 e31 i/o7 i/o11 297 f24 g28 i/o8 i/o12 296 e25 g29 vcc vcc vcc (1) vcc (1) gnd gnd gnd (1) gnd (1) i/o13 f30 i/o14 f31 i/o7 i/o7 i/o9 i/o15 8 10 d2 8 295 d26 h28 i/o8 i/o8 i/o10 i/o16 9 11 g6 9 294 g24 h29 i/o9 i/o11 i/o17 12 e4 10 293 f25 g30 i/o10 i/o12 i/o18 13 d1 11 292 f26 h30 gnd gnd (1) i/o19 i/o20 i/o11 i/o13 i/o21 e3 12 291 h23 j28 i/o12 i/o14 i/o22 e2 13 290 h24 j29 i/o15 i/o23 289 g25 h31 i/o16 i/o24 288 g26 j30 gnd gnd gnd gnd 8 10 14 gnd* 14 287 gnd (1) gnd (1) i/o9, fck1 i/o13, fck1 i/o17, fck1 i/o25, fck1 9 11 15 f5 15 286 j23 k28 i/o10 i/o14 i/o18 i/o26 10 12 16 e1 16 285 j24 k29 i/o11 (a20) i/o15 (a20) i/o19 (a20) i/o27 (a20) 17 9 6 11 13 17 f4 17 284 h25 k30 i/o12 (a21) i/o16 (a21) i/o20 (a21) i/o28 (a21) 18 10 7 12 14 18 f3 18 283 k23 k31 vcc vcc vcc vcc* 19 282 vcc (1) vcc (1) i/o17 i/o21 i/o29 f2 20 280 k24 l29 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 33 i/o18 i/o22 i/o30 f1 21 279 j25 l30 gnd gnd* i/o31 m30 i/o32 m28 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 i/o33 j26 m29 i/o34 l23 m31 i/o23 i/o35 278 l24 n31 i/o24 i/o36 277 k25 n28 gnd gnd 22 gnd (1) gnd (1) vcc vcc (1) vcc (1) i/o37 n29 i/o38 n30 i/o25 i/o39 276 l25 p30 i/o26 i/o40 275 l26 p28 i/o19 i/o27 i/o41 19 g4 23 274 m23 p29 i/o20 i/o28 i/o42 20 g3 24 273 m24 r31 gnd gnd (1) i/o13 i/o21 i/o29 i/o43 13 15 21 g2 25 272 m25 r30 i/o14 i/o22 i/o30 i/o44 11 8 14 16 22 g1 26 271 m26 r28 i/o45 i/o46 i/o15 (a22) i/o23 (a22) i/o31 (a22) i/o47 (a22) 19 12 9 15 17 23 g5 27 270 n24 r29 i/o16 (a23) i/o24 (a23) i/o32 (a23) i/o48 (a23) 20 13 10 16 18 24 h3 28 269 n25 t31 gnd gnd gnd gnd 21 14 11 17 19 25 gnd (1) 29 268 gnd (1) gnd (1) vcc vcc vcc vcc 22 15 12 18 20 26 vcc (1) 30 267 vcc (1) vcc (1) i/o17 i/o25 i/o33 i/o49 23 16 13 19 21 27 h4 31 266 n26 t30 i/o18 i/o26 i/o34 i/o50 24 17 14 20 22 28 h5 32 265 p25 t29 i/o51 i/o52 i/o19 i/o27 i/o35 i/o53 18 15 21 23 29 j2 33 264 p23 u31 i/o20 i/o28 i/o36 i/o54 22 24 30 j1 34 263 p24 u30 gnd gnd (1) i/o29 i/o37 i/o55 31 j3 35 262 r26 u28 i/o30 i/o38 i/o56 32 j4 36 261 r25 u29 i/o39 i/o57 260 r24 v30 i/o40 i/o58 259 r23 v29 i/o59 v28 i/o60 w31 vcc vcc (1) vcc (1) gnd gnd 37 gnd (1) gnd (1) i/o41 i/o61 258 t26 w30 i/o42 i/o62 257 t25 w29 at40k05 at40k10 at40k20 at40k40 left side (top to bottom) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 34 i/o63 w28 i/o64 y31 i/o65 t24 y30 i/o66 u25 y29 gnd gnd (1) i/o31 i/o43 i/o67 j5 38 256 t23 y28 i/o32 i/o44 i/o68 k1 39 255 v26 aa30 vcc vcc vcc vcc (1) 40 253 vcc (1) vcc (1) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 i/o21 i/o33 i/o45 i/o69 25 19 16 23 25 33 k2 41 252 u24 aa29 i/o22 i/o34 i/o46 i/o70 26 20 17 24 26 34 k3 42 251 v25 ab31 i/o23 i/o35 i/o47 i/o71 25 27 35 j6 43 250 v24 ab30 i/o24, fck2 i/o36, fck2 i/o48, fck2 i/o72, fck2 26 28 36 l1 44 249 u23 ab29 gnd gnd gnd gnd 27 29 37 gnd* 45 248 gnd (1) gnd (1) i/o49 i/o73 247 y26 ab28 i/o50 i/o74 246 w25 ac30 i/o37 i/o51 i/o75 l2 46 245 w24 ac29 i/o38 i/o52 i/o76 k4 47 244 v23 ac28 i/o77 i/o78 gnd gnd (1) vcc (1) i/o79 ad31 i/o80 ad30 i/o39 i/o53 i/o81 38 l3 48 243 aa26 ad29 i/o40 i/o54 i/o82 39 m1 49 242 y25 ad28 i/o25 i/o41 i/o55 i/o83 30 40 k5 50 241 y24 ae30 i/o26 i/o42 i/o56 i/o84 31 41 m2 51 240 aa25 ae29 gnd gnd gnd (1) gnd (1) vcc vcc vcc (1) vcc (1) i/o57 i/o85 239 ab25 af31 i/o58 i/o86 238 aa24 ae28 i/o87 af30 i/o88 af29 i/o27 i/o43 i/o59 i/o89 27 21 18 28 32 42 l4 52 237 y23 ag31 i/o28 i/o44 i/o60 i/o90 22 19 29 33 43 n1 53 236 ac26 af28 gnd gnd (1) i/o91 ad26 ag30 i/o92 ac25 ag29 i/o29 i/o45 i/o61 i/o93 30 34 44 m3 54 235 aa23 ah31 i/o30 i/o46 i/o62 i/o94 31 35 45 n2 55 234 ab24 ag28 i/o31 (/ots) i/o47 (/ots) i/o63 (/ots) i/o95 (/ots) 28 23 20 32 36 46 k6 56 233 ad25 ah30 at40k05 at40k10 at40k20 at40k40 left side (top to bottom) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 35 i/o32, gck2 i/o48, gck2 i/o64, gck2 i/o96, gck2 29 24 21 33 37 47 p1 57 232 ac24 aj30 m1 m1 m1 m1 30 25 22 34 38 48 n3 58 231 ab23 ah29 gnd gnd gnd gnd 31 26 23 35 39 49 gnd (1) 59 230 gnd (1) gnd (1) m0 m0 m0 m0 32 27 24 36 40 50 p2 60 229 ad24 ah28 at40k05 at40k10 at40k20 at40k40 left side (top to bottom) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 at40k05 at40k10 at40k20 at40k40 bottom side (left to right) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 vcc vcc vcc vcc 33 28 25 37 41 55 vcc* 61 228 vcc (1) vcc (1) m2 m2 m2 m2 34 29 26 38 42 56 m4 62 227 ac23 aj28 i/o33, gck3 i/o49, gck3 i/o65, gck3 i/o97, gck3 35 30 27 39 43 57 r2 63 226 ae24 ak29 i/o34 (hdc) i/o50 (hdc) i/o66 (hdc) i/o98 (hdc) 36 31 28 40 44 58 p3 64 225 ad23 ah27 i/o35 i/o51 i/o67 i/o99 41 45 59 l5 65 224 ac22 ak28 i/o36 i/o52 i/o68 i/o100 42 46 60 n4 66 223 af24 aj27 i/o37 i/o53 i/o69 i/o101 32 29 43 47 61 r3 67 222 ad22 al28 i/o38 (ldc) i/o54 (ldc) i/o70 (ldc) i/o102 (ldc) 37 33 30 44 48 62 p4 68 221 ae23 ah26 gnd gnd (1) i/o103 ak27 i/o104 aj26 i/o105 ac21 al27 i/o106 ad21 ah25 i/o71 i/o107 220 ae22 ak26 i/o72 i/o108 219 af23 al26 vcc vcc vcc (1) vcc (1) gnd gnd gnd (1) gnd (1) i/o39 i/o55 i/o73 i/o109 49 63 k7 69 218 ad20 ah24 i/o40 i/o56 i/o74 i/o110 50 64 m5 70 217 ae21 aj25 i/o57 i/o75 i/o111 65 r4 71 216 af21 ak25 i/o58 i/o76 i/o112 66 n5 72 215 ac19 aj24 i/o113 ah23 i/o114 ak24 vcc (1) gnd gnd (1) i/o115 i/o116 i/o59 i/o77 i/o117 p5 73 214 ad19 al24 i/o60 i/o78 i/o118 l6 74 213 ae20 ah22 i/o79 i/o119 212 af20 aj23 i/o80 i/o120 211 ac18 ak23 gnd gnd gnd gnd 45 51 67 gnd (1) 75 210 gnd (1) gnd (1) note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 36 i/o41 i/o61 i/o81 i/o121 46 52 68 r5 76 209 ad18 aj22 i/o42 i/o62 i/o82 i/o122 47 53 69 m6 77 208 ae19 ak22 i/o43 i/o63 i/o83 i/o123 38 34 31 48 54 70 n6 78 207 ac17 al22 i/o44 i/o64 i/o84 i/o124 39 35 32 49 55 71 p6 79 206 ad17 aj21 vcc vcc vcc vcc (1) 80 204 vcc (1) vcc (1) i/o65 i/o85 i/o125 72 r6 81 203 ae18 ah20 i/o66 i/o86 i/o126 73 m7 82 202 af18 ak21 gnd gnd (1) i/o127 aj20 i/o128 ah19 i/o129 ac16 ak20 i/o130 ad16 aj19 i/o87 i/o131 201 ae17 al20 i/o88 i/o132 200 ae16 ah18 gnd gnd 83 gnd (1) gnd (1) vcc vcc (1) vcc (1) i/o89 i/o133 199 af16 ak19 i/o90 i/o134 198 ac15 aj18 i/o67 i/o91 i/o135 n7 84 197 ad15 al19 i/o68 i/o92 i/o136 p7 85 196 ae15 ak18 i/o45 i/o69 i/o93 i/o137 36 33 50 56 74 r7 86 195 af15 ah17 i/o46 i/o70 i/o94 i/o138 37 34 51 57 75 l7 87 194 ad14 aj17 gnd gnd (1) i/o139 i/o140 i/o141 ak17 i/o142 al17 i/o47 (d15) i/o71 (d15) i/o95 (d15) i/o143 (d15) 40 38 35 52 58 76 n8 88 193 ae14 aj16 i/o48 (init) i/o72 (init) i/o96 (init) i/o144 (init) 41 39 36 53 59 77 p8 89 192 af14 ak16 vcc vcc vcc vcc 42 40 37 54 60 78 vcc (1) 90 191 vcc (1) vcc (1) gnd gnd gnd gnd 43 41 38 55 61 79 gnd (1) 91 190 gnd (1) gnd (1) i/o49 (d14) i/o73 (d14) i/o97 (d14) i/o145 (d14) 44 42 39 56 62 80 l8 92 189 ae13 al16 i/o50 (d13) i/o74 (d13) i/o98 (d13) i/o146 (d13) 45 43 40 57 63 81 p9 93 188 ac13 ah15 i/o147 al15 i/o148 aj15 i/o149 i/o150 gnd gnd (1) i/o51 i/o75 i/o99 i/o151 44 41 58 64 82 r9 94 187 ad13 ak15 i/o52 i/o76 i/o100 i/o152 45 42 59 65 83 n9 95 186 af12 aj14 i/o77 i/o101 i/o153 84 m9 96 185 ae12 ah14 i/o78 i/o102 i/o154 85 l9 97 184 ad12 ak14 i/o103 i/o155 183 ac12 al13 at40k05 at40k10 at40k20 at40k40 bottom side (left to right) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 37 i/o104 i/o156 182 af11 ak13 vcc vcc (1) vcc (1) gnd gnd 98 gnd (1) gnd (1) i/o105 i/o157 181 ae11 aj13 i/o106 i/o158 180 ad11 ah13 i/o159 ae10 al12 i/o160 ac11 ak12 i/o161 aj12 i/o162 ak11 gnd gnd (1) i/o79 i/o107 i/o163 r10 99 179 af9 ah12 i/o80 i/o108 i/o164 p10 100 178 ad10 aj11 vcc vcc vcc vcc (1) 101 177 vcc (1) vcc (1) i/o53 (d12) i/o81 (d12) i/o109 (d12) i/o165 (d12) 46 46 43 60 66 86 n10 102 175 ae9 al10 i/o54 (d11) i/o82 (d11) i/o110 (d11) i/o166 (d11) 47 47 44 61 67 87 k9 103 174 ad9 ak10 i/o55 i/o83 i/o111 i/o167 62 68 88 r11 104 173 ac10 aj10 i/o56 i/o84 i/o112 i/o168 63 69 89 p11 105 172 af7 ak9 gnd gnd gnd gnd 64 70 90 gnd (1) 106 171 gnd (1) gnd (1) i/o113 i/o169 170 ae8 al8 i/o114 i/o170 169 ad8 ah10 i/o85 i/o115 i/o171 m10 107 168 ac9 aj9 i/o86 i/o116 i/o172 n11 108 167 af6 ak8 i/o173 i/o174 gnd gnd (1) vcc (1) i/o175 aj8 i/o176 ah9 i/o87 i/o117 i/o177 91 r12 109 166 ae7 ak7 i/o88 i/o118 i/o178 92 l10 110 165 ad7 al6 i/o57 i/o89 i/o119 i/o179 71 93 p12 111 164 ae6 aj7 i/o58 i/o90 i/o120 i/o180 72 94 m11 112 163 ae5 ah8 gnd gnd gnd (1) gnd (1) vcc vcc vcc (1) vcc (1) i/o121 i/o181 162 ad6 ak6 i/o122 i/o182 161 ac7 al5 i/o59 (d10) i/o91 (d10) i/o123 (d10) i/o183 (d10) 48 48 45 65 73 95 r13 113 160 af4 ah7 i/o60 (d9) i/o92 (d9) i/o124 (d9) i/o184 (d9) 49 49 46 66 74 96 n12 114 159 af3 aj6 i/o185 ae4 ak5 at40k05 at40k10 at40k20 at40k40 bottom side (left to right) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 38 i/o186 ac6 al4 gnd gnd (1) i/o187 ah6 i/o188 aj5 i/o61 i/o93 i/o125 i/o189 67 75 97 p13 115 158 ad5 ak4 i/o62 i/o94 i/o126 i/o190 68 76 98 k10 116 157 ae3 ah5 i/o63 (d8) i/o95 (d8) i/o127 (d8) i/o191 (d8) 50 50 47 69 77 99 r14 117 156 ad4 ak3 i/o64, gck4 i/o96, gck4 i/o128, gck4 i/o192 ,gck4 51 51 48 70 78 100 n13 118 155 ac5 aj4 gnd gnd gnd gnd 52 52 49 71 79 101 gnd (1) 119 154 gnd (1) gnd (1) /con /con /con /con 53 53 50 72 80 103 p14 120 153 ad3 ah4 at40k05 at40k10 at40k20 at40k40 bottom side (left to right) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 at40k05 at40k10 at40k20 at40k40 right side (bottom to top) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 vcc vcc vcc vcc 54 54 51 73 81 106 vcc (1) 121 152 vcc (1) vcc (1) /reset /reset /reset /reset 55 55 52 74 82 108 m12 122 151 ac4 ah3 i/o65 (d7) i/o97 (d7) i/o129 (d7) i/o193 (d7) 56 56 53 75 83 109 p15 123 150 ad2 aj2 i/o66, gck5 i/o98, gck5 i/o130, gck5 i/o194, gck5 57 57 54 76 84 110 n14 124 149 ac3 ag4 i/o67 i/o99 i/o131 i/o195 77 85 111 l11 125 148 ab4 ag3 i/o68 i/o100 i/o132 i/o196 78 86 112 m13 126 147 ad1 ah2 i/o197 ab3 ah1 i/o198 ac2 af4 gnd gnd (1) i/o101 i/o133 i/o199 n15 127 146 aa4 af3 i/o102 i/o134 i/o200 m14 128 145 aa3 ag2 i/o201 ag1 i/o202 ae4 i/o135 i/o203 144 ab2 ae3 i/o136 i/o204 143 ac1 af2 vcc vcc vcc (1) vcc (1) gnd gnd gnd (1) gnd (1) i/o69 (d6) i/o103 (d6) i/o137 (d6) i/o205 (d6) 58 58 55 79 87 113 j10 129 142 y3 af1 i/o70 i/o104 i/o138 i/o206 59 56 80 88 114 l12 130 141 aa2 ad4 i/o71 i/o105 i/o139 i/o207 89 115 m15 131 140 aa1 ad3 i/o72 i/o106 i/o140 i/o208 90 116 l13 132 139 w4 ae2 i/o209 ad2 i/o210 ac4 vcc (1) gnd gnd (1) note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 39 i/o211 i/o212 i/o107 i/o141 i/o213 117 l14 133 138 w3 ac3 i/o108 i/o142 i/o214 118 k11 134 137 y2 ad1 i/o143 i/o215 136 y1 ac2 i/o144 i/o216 135 v4 ab4 gnd gnd gnd gnd 81 91 119 gnd (1) 135 134 gnd (1) gnd (1) i/o109 i/o145 i/o217 l15 136 133 v3 ab3 i/o110 i/o146 i/o218 k12 137 132 w2 ab2 i/o73, fck3 i/o111, fck3 i/o147, fck3 i/o219, fck3 82 92 120 k13 138 131 u4 ab1 i/o74 i/o112 i/o148 i/o220 83 93 121 k14 139 130 u3 aa3 vcc vcc vcc vcc (1) 140 129 vcc (1) vcc (1) i/o75 (d5) i/o113 (d5) i/o149 (d5) i/o221 (d5) 59 60 57 84 94 122 k15 141 127 v2 aa2 i/o76 (cs0) i/o114 (cs0) i/o150 (cs0) i/o222 (cs0) 60 61 58 85 95 123 j12 142 126 v1 y2 gnd gnd (1) i/o223 t4 y4 i/o224 t3 y3 i/o225 y1 i/o226 w1 i/o151 i/o227 125 u2 w4 i/o152 i/o228 124 t2 w3 gnd gnd 143 gnd (1) gnd (1) vcc vcc (1) vcc (1) i/o229 w2 i/o230 v2 i/o153 i/o231 123 t1 v4 i/o154 i/o232 122 r4 v3 i/o115 i/o155 i/o233 124 j13 144 121 r3 u1 i/o116 i/o156 i/o234 125 j14 145 120 r2 u2 gnd gnd (1) i/o77 i/o117 i/o157 i/o235 62 59 86 96 126 j15 146 119 r1 u4 i/o78 i/o118 i/o158 i/o236 63 60 87 97 127 j11 147 118 p3 u3 i/o237 i/o238 i/o79(d4) i/o119(d4) i/o159(d4) i/o239(d4) 61 64 61 88 98 128 h13 148 117 p2 t1 i/o80 i/o120 i/o160 i/o240 62 65 62 89 99 129 h14 149 116 p1 t2 vcc vcc vcc vcc 63 66 63 90 100 130 vcc (1) 150 115 vcc (1) vcc (1) gnd gnd gnd gnd 64 67 64 91 101 131 gnd (1) 151 114 gnd (1) gnd (1) i/o81 (d3) i/o121 (d3) i/o161 (d3) i/o241 (d3) 65 68 65 92 102 132 h12 152 113 n2 t3 i/o82 (/check) i/o122 (/check) i/o162 (/check) i/o242 (/check) 66 69 66 93 103 133 h11 153 112 n4 r1 i/o243 at40k05 at40k10 at40k20 at40k40 right side (bottom to top) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 40 i/o244 i/o83 i/o123 i/o163 i/o245 70 67 94 104 134 g14 154 111 n3 r2 i/o84 i/o124 i/o164 i/o246 95 105 135 g15 155 110 m1 r4 gnd gnd (1) i/o125 i/o165 i/o247 136 g13 156 109 m2 r3 i/o126 i/o166 i/o248 137 g12 157 108 m3 p2 i/o167 i/o249 107 m4 p3 i/o168 i/o250 106 l1 p4 i/o251 n1 i/o252 n2 vcc vcc (1) vcc (1) gnd gnd 158 gnd (1) gnd (1) i/o169 i/o253 105 l2 n3 i/o170 i/o254 104 l3 n4 i/o255 k2 m1 i/o256 l4 m2 i/o257 m3 i/o258 m4 gnd gnd (1) i/o85 (d2) i/o127 (d2) i/o171 (d2) i/o259 (d2) 67 71 68 96 106 138 g11 159 103 j1 l2 i/o86 i/o128 i/o172 i/o260 68 72 69 97 107 139 f15 160 102 k3 l3 vcc vcc vcc vcc (1) 161 101 vcc (1) vcc (1) i/o87 i/o129 i/o173 i/o261 98 108 140 f14 162 99 j2 k1 i/o88, fck4 i/o130, fck4 i/o174, fck4 i/o262, fck4 99 109 141 f13 163 98 j3 k2 i/o131 i/o175 i/o263 g10 164 97 k4 k3 i/o132 i/o176 i/o264 e15 165 96 g1 k4 gnd gnd gnd gnd 100 110 142 gnd (1) 166 95 gnd (1) gnd (1) i/o177 i/o265 94 h2 j2 i/o178 i/o266 93 h3 j3 i/o133 i/o179 i/o267 e14 167 92 j4 j4 i/o134 i/o180 i/o268 f12 168 91 f1 h1 i/o269 i/o270 gnd gnd (1) i/o135 i/o181 i/o271 143 e13 169 90 g2 h2 i/o136 i/o182 i/o272 144 d15 170 89 g3 h3 i/o89 i/o137 i/o183 i/o273 111 145 f11 171 88 f2 h4 at40k05 at40k10 at40k20 at40k40 right side (bottom to top) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 41 i/o90 i/o138 i/o184 i/o274 112 146 d14 172 87 e2 g2 i/o275 g3 i/o276 f1 gnd gnd gnd (1) gnd (1) vcc vcc vcc (1) vcc (1) i/o91 (d1) i/o139 (d1) i/o185 (d1) i/o277 (d1) 69 73 70 101 113 147 e12 173 86 f3 g4 i/o92 i/o140 i/o186 i/o278 70 74 71 102 114 148 c15 174 85 g4 f2 i/o279 d1 f3 i/o280 c1 e1 i/o281 f4 i/o282 e2 gnd gnd (1) i/o187 i/o283 84 d2 e3 i/o188 i/o284 83 f4 d1 i/o93 i/o141 i/o189 i/o285 103 115 149 d13 175 82 e3 e4 i/o94 i/o142 i/o190 i/o286 104 116 150 c14 176 81 c2 d2 i/o95 (d0) i/o143 (d0) i/o191 (d0) i/o287 (d0) 71 75 72 105 117 151 f10 177 80 d3 c2 i/o96, gck6 (/csout) i/o144, gck6 (/csout) i/o192, gck6 (/csout) i/o288, gck6 (/csout) 72 76 73 106 118 152 b15 178 79 e4 d3 cclk cclk cclk cclk 73 77 74 107 119 153 c13 179 78 c3 d4 vcc vcc vcc vcc 74 78 75 108 120 154 vcc (1) 180 77 vcc (1) vcc (1) at40k05 at40k10 at40k20 at40k40 right side (bottom to top) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 at40k05 at40k10 at40k20 at40k40 top side (right to left) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 gnd gnd gnd gnd 76 80 77 110 122 160 gnd (1) 182 75 gnd (1) gnd (1) i/o97 (a0) i/o145 (a0) i/o193 (a0) i/o289 (a0) 77 81 78 111 123 161 a14 183 74 b3 b3 i/o98, gck7 (a1) i/o146, gck7 (a1) i/o194, gck7 (a1) i/o290, gck7 (a1) 78 82 79 112 124 162 b13 184 73 c4 d5 i/o99 i/o147 i/o195 i/o291 113 125 163 e11 185 72 d5 b4 i/o100 i/o148 i/o196 i/o292 114 126 164 c12 186 71 a3 c5 i/o293 a4 i/o294 d6 gnd gnd (1) i/o295 c5 b5 i/o296 b4 c6 i/o101 (/cs1,a2) i/o149 (/cs1,a2) i/o197 (/cs1,a2) i/o297 (/cs1,a2) 79 83 80 115 127 165 a13 187 70 d6 a5 i/o102 (a3) i/o150 (a3) i/o198 (a3) i/o298 (a3) 80 84 81 116 128 166 b12 188 69 c6 d7 i/o199 i/o299 68 b5 b6 i/o200 i/o300 67 a4 a6 vcc vcc vcc (1) vcc (1) note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 42 gnd gnd gnd (1) gnd (1) i/o151 i/o201 i/o301 75 79 76 109 121 159 f9 189 66 c7 d8 i/o152 i/o202 i/o302 d11 190 65 b6 c7 i/o103 i/o153 i/o203 i/o303 117 129 167 a12 191 64 a6 b7 i/o104 i/o154 i/o204 i/o304 75 (2) 79 (2) 76 (2) 109 (2) 130 168 c11 192 63 d8 d9 i/o305 c8 b8 i/o306 a8 vcc (1) gnd gnd (1) i/o307 i/o308 i/o155 i/o205 i/o309 169 b11 193 62 b7 d10 i/o156 i/o206 i/o310 170 e10 194 61 a7 c9 i/o207 i/o311 195 60 d9 b9 i/o208 i/o312 59 c9 c10 gnd gnd gnd gnd 118 131 171 gnd (1) 196 58 gnd (1) gnd (1) v i/o105 i/o157 i/o209 i/o313 119 132 172 a11 197 57 b8 b10 i/o106 i/o158 i/o210 i/o314 120 133 173 d10 198 56 d10 a10 i/o159 i/o211 i/o315 c10 199 55 c10 c11 i/o160 i/o212 i/o316 b10 200 54 b9 d12 vcc vcc vcc vcc* 201 52 vcc (1) vcc (1) i/o213 i/o317 51 a9 b11 i/o214 i/o318 50 d11 c12 gnd gnd (1) i/o319 d13 i/o320 b12 i/o321 c11 c13 i/o322 b10 a12 i/o215 i/o323 49 b11 d14 i/o216 i/o324 48 a11 b13 gnd gnd gnd (1) gnd (1) vcc vcc (1) vcc (1) i/o107 (a4) i/o161 (a4) i/o217 (a4) i/o325 (a4) 81 85 82 121 134 174 a10 202 47 d12 c14 i/o108 (a5) i/o162 (a5) i/o218 (a5) i/o326 (a5) 82 86 83 122 135 175 d9 203 46 c12 a13 i/o163 i/o219 i/o327 176 c9 205 45 b12 b14 i/o164 i/o220 i/o328 136 177 b9 206 44 a12 d15 i/o109 i/o165 i/o221 i/o329 87 84 123 137 178 a9 207 43 c13 c15 i/o110 i/o166 i/o222 i/o330 88 85 124 138 179 e9 208 42 b13 b15 at40k05 at40k10 at40k20 at40k40 top side (right to left) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 notes: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin. 2. this applies to the at40k05 only.
at40k 43 gnd gnd (1) i/o331 i/o332 i/o333 a15 i/o334 c16 i/o111 (a6) i/o167 (a6) i/o223 (a6) i/o335 (a6) 83 89 86 125 139 180 c8 209 41 a13 b16 i/o112 (a7) i/o168 (a7) i/o224 (a7) i/o336 (a7) 84 90 87 126 140 181 b8 210 40 b14 a16 gnd gnd gnd gnd 1 91 88 127 141 182 gnd (1) 211 39 gnd (1) gnd (1) vcc vcc vcc vcc 2 92 89 128 142 183 vcc (1) 212 38 vcc (1) vcc (1) i/o113 (a8) i/o169 (a8) i/o225 (a8) i/o337 (a8) 3 93 90 129 143 184 e8 213 37 d14 d17 i/o114 (a9) i/o170 (a9) i/o226 (a9) i/o338 (a9) 4 94 91 130 144 185 b7 214 36 c14 a17 i/o339 c17 i/o340 b17 i/o341 i/o342 gnd gnd (1) i/o115 i/o171 i/o227 i/o343 95 92 131 145 186 a7 215 35 a15 c18 i/o116 i/o172 i/o228 i/o344 96 93 132 146 187 c7 216 34 b15 d18 i/o173 i/o229 i/o345 188 d7 217 33 c15 b18 i/o174 i/o230 i/o346 189 e7 218 32 d15 a19 i/o117 (a10) i/o175 (a10) i/o231 (a10) i/o347 (a10) 5 97 94 133 147 190 a6 220 31 a16 b19 i/o118 (a11) i/o176 (a11) i/o232 (a11) i/o348 (a11) 6 98 95 134 148 191 b6 221 30 b16 c19 vcc vcc (1) vcc (1) gnd gnd gnd (1) gnd (1) i/o233 i/o349 29 c16 d19 i/o234 i/o350 28 b17 a20 i/o351 d16 b20 i/o352 a18 c20 i/o353 b21 i/o354 d20 gnd gnd (1) i/o235 i/o355 27 c17 c21 i/o236 i/o356 26 b18 a22 vcc vcc vcc vcc (1) 222 25 vcc (1) vcc (1) i/o177 i/o237 i/o357 c6 223 23 c18 b22 i/o178 i/o238 i/o358 f7 224 22 d17 c22 i/o119 i/o179 i/o239 i/o359 135 149 192 a5 225 21 a20 b23 i/o120 i/o180 i/o240 i/o360 136 150 193 b5 226 20 b19 a24 at40k05 at40k10 at40k20 at40k40 top side (right to left) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 44 gnd gnd gnd gnd 137 151 194 gnd* 227 19 gnd (1) gnd (1) i/o241 i/o361 18 c19 d22 i/o242 i/o362 17 d18 c23 i/o181 i/o243 i/o363 195 d6 228 16 a21 b24 i/o182 i/o244 i/o364 196 c5 229 15 b20 c24 i/o365 i/o366 gnd gnd (1) i/o367 d23 i/o368 b25 i/o121 i/o183 i/o245 i/o369 152 197 a4 230 14 c20 a26 i/o122 i/o184 i/o246 i/o370 153 198 e6 231 13 b21 c25 i/o123 (a12) i/o185 (a12) i/o247 (a12) i/o371 (a12) 7 99 96 138 154 199 b4 232 12 b22 d24 i/o124 (a13) i/o186 (a13) i/o248 (a13) i/o372 (a13) 8 100 97 139 155 200 d5 233 10 c21 b26 gnd gnd gnd* gnd* vcc vcc vcc* vcc* i/o249 i/o373 9d20a27 i/o250 i/o374 8a23d25 i/o375 a24 c26 i/o376 b23 b27 i/o377 a28 i/o378 d26 gnd gnd* i/o187 i/o251 i/o379 a3 234 7 d21 c27 i/o188 i/o252 i/o380 c4 235 6 c22 b28 i/o125 i/o189 i/o253 i/o381 140 156 201 b3 236 5 b24 d27 i/o126 i/o190 i/o254 i/o382 141 157 202 f6 237 4 c23 b29 i/o127 (a14) i/o191 (a14) i/o255 (a14) i/o383 (a14) 9 1 98 142 158 203 a2 238 3 d22 c28 i/o128, gck8 (a15) i/o192, gck8 (a15) i/o256, gck8 (a15) i/o384, gck8 (a15) 10 2 99 143 159 204 c3 239 2 c24 d28 vcc vcc vcc vcc 11 3 100 144 160 205 vcc* 240 1 vcc (1) vcc (1) at40k05 at40k10 at40k20 at40k40 top side (right to left) 128 i/o 192 i/o 256 i/o 384 i/o pc84 rq100 vq100 tq144 pq160 pq208 bg225 pq240 pq304 bg352 bg432 note: 1. pads labelled gnd or vcc are internally bonded to ground or vcc planes within the package. they have no direct con- nection to any specific package pin.
at40k 45 figure 15. at40k20 pad ring gnd i/o1,gck1 (a16) i/o2 (a17) i/o3 i/o4 i/o5 (a18) i/o6 (a19) i/o7 i/o8 vcc gnd i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 gnd i/o17,fck1 i/o18 i/o19 (a20) i/o20 (a21) vcc i/o21 i/o22 i/o23 i/o24 gnd? i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 (a22) i/o32 (a23) gnd vcc i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 i/o40 gnd? i/o41 i/o42 i/o43 i/o44 vcc i/o45 i/o46 i/o47 i/o48,fck2 gnd i/o49 i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 i/o56 gnd vcc i/o57 i/o58 i/o59 i/o60 i/o61 i/o62 i/o63 (/ots) i/o64,gck2 m1 gnd m0 vcc m2 i/o65,gck3 i/o66 (hdc) i/o67 i/o68 i/o69 i/o70 (ldc) i/o71 i/o72 vcc gnd i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 i/o79 i/o80 gnd i/o81 i/o82 i/o83 i/o84 vcc i/o85 i/o86 i/o87 i/o88 gnd? i/o89 i/o90 i/o91 i/o92 i/o93 i/o94 i/o95 (d15) i/o96 (/err/init) vcc gnd i/o97 (d14) i/o98 (d13) i/o99 i/o100 i/o101 i/o102 i/o103 i/o104 gnd? i/o105 i/o106 i/o107 i/o108 vcc i/o109 (d12) i/o110 (d11) i/o111 i/o112 gnd i/o113 i/o114 i/o115 i/o116 i/o117 i/o118 i/o119 i/o120 gnd vcc i/o121 i/o122 i/o123 (d10) i/o124 (d9) i/o125 i/o126 i/o127 (d8) i/o128,gck4 gnd /con vcc /reset i/o129 (d7) i/o130,gck5 i/o131 i/o132 i/o133 i/o134 i/o135 i/o136 vcc gnd i/o137 (d6) i/o138 i/o139 i/o140 i/o141 i/o142 i/o143 i/o144 gnd i/o145 i/o146 i/o147,fck3 i/o148 vcc i/o149 (d5) i/o150 (/cs0) gnd? i/o151 i/o152 gnd i/o153 i/o154 i/o155 i/o156 i/o157 i/o158 i/o159 (d4) i/o160 vcc gnd i/o161 (d3) i/o162 (/check) i/o163 i/o164 i/o165 i/o166 i/o167 i/o168 gnd? i/o169 i/o170 i/o171 (d2) i/o172 vcc i/o173 i/o174,fck4 i/o175 i/o176 gnd i/o177 i/o178 i/o179 i/o180 i/o181 i/o182 i/o183 i/o184 gnd vcc i/o185 (d1) i/o186 i/o187 i/o188 i/o189 i/o190 i/o191 (d0) i/o192,gck6 (/cscout) cclk vcc tstclk gnd i/o193 (a0) i/o194,gck7 (a1) i/o195 i/o196 i/o197 (/cs1,a2) i/o198 (a3) i/o199 i/o200 vcc gnd i/o201 i/o202 i/o203 i/o204 i/o205 i/o206 i/o207 i/o208 gnd i/o209 i/o210 i/o211 i/o212 vcc i/o213 i/o214 i/o215 i/o216 gnd i/o217 (a4) i/o218 (a5) i/o219 i/o220 i/o221 i/o222 i/o223 (a6) i/o224 (a7) gnd vcc i/o225 (a8) i/o226 (a9) i/o227 i/o228 i/o229 i/o230 i/o231 (a10) i/o232 (a11) gnd i/o233 i/o234 i/o235 i/o236 vcc i/o237 i/o238 i/o239 i/o240 gnd i/o241 i/o242 i/o243 i/o244 i/o245 i/o246 i/o247 (a12) i/o248 (a13) gnd vcc i/o249 i/o250 i/o251 i/o252 i/o253 i/o254 i/o255 (a14) i/o256,gck8 (a15) vcc
at40k 46 at40k05 ordering information usable gates speed grade (ns) ordering code package operation range 5,000-10,000 2 at40k05-2ajc at40k05-2aqc at40k05-2bqc at40k05-2cqc at40k05-2dqc 84j 100q 144q 160q 208q 5v commercial (0 c to 70 c) 5,000-10,000 2 at40k05-2aji at40k05-2aqi at40k05-2bqi at40k05-2cqi at40k05-2dqi 84j 100q 144q 160q 208q 5v industrial (-40 c to 85 c) usable gates speed grade (ns) ordering code package operation range 5,000-10,000 3 at40k05lv-3ajc at40k05lv-3aqc at40k05lv-3bqc at40k05lv-3cqc at40k05lv-3dqc 84j 100q 144q 160q 208q 3.3v commercial (0 c to 20 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q 100-lead, very thin (1.0 mm) plastic gull wing quad flat package (vqfp) 100rq 100-lead, rectangular plastic plastic gull wing quad flat package (rqpd) 144q 144-lead, thin (1.4 mm) plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic gull wing quad flat package (pqfp) 208q 208-lead, plastic gull wing quad flat package (pqfp) 225g 225-lead, ball grid array package (bga) 240q 240-lead, plastic gull wing quad flat package (pqfp) 304q 304-lead, plastic gull wing quad flat package (pqfp) 352g 352-ball, ball grid array package (bga) 432g 432-ball, ball grid array package (bga)
at40k 47 at40k10 ordering information usable gates speed grade (ns) ordering code package operation range 10,000-20,000 2 at40k10-2ajc at40k10-2aqc at40k10-2rqc at40k10-2bqc at40k10-2cqc at40k10-2dqc AT40K10-2EQC at40k10-2agc 84j 100q 100rq 144q 160q 208q 240q 225g 5v commercial (0 c to 70 c) 10,000-20,000 2 at40k10-2aji at40k10-2aqi at40k10-2bqi at40k10-2cqi at40k10-2dqi at40k10-2eqi at40k10-2agi 84j 100q 144q 160q 208q 240q 225g 5v industrial (-40 c to 85 c) usable gates speed grade (ns) ordering code package operation range 10,000-20,000 3 at40k10lv-3ajc at40k10lv-3aqc at40k10lv-3rqc at40k10lv-3bqc at40k10lv-3cqc at40k10lv-3dqc at40k10lv-3eqc at40k10lv-3agc 84j 100q 100rq 144q 160q 208q 240q 225g 3.3v commercial (0 c to 20 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q 100-lead, very thin (1.0 mm) plastic gull wing quad flat package (vqfp) 100rq 100-lead, rectangular plastic plastic gull wing quad flat package (rqpd) 144q 144-lead, thin (1.4 mm) plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic gull wing quad flat package (pqfp) 208q 208-lead, plastic gull wing quad flat package (pqfp) 225g 225-lead, ball grid array package (bga) 240q 240-lead, plastic gull wing quad flat package (pqfp) 304q 304-lead, plastic gull wing quad flat package (pqfp) 352g 352-ball, ball grid array package (bga) 432g 432-ball, ball grid array package (bga)
at40k 48 at40k20 ordering information usable gates speed grade (ns) ordering code package operation range 20,000-30,000 2 at40k20-2ajc at40k20-2aqc at40k20-2bqc at40k20-2cqc at40k20-2dqc at40k20-2eqc at40k20-2fqc at40k20-2bgc at40k20-2agc 84j 100q 144q 160q 208q 240q 304q 352g 225g 5v commercial (0 c to 70 c) 20,000-30,000 2 at40k20-2aji at40k20-2bqi at40k20-2cqi at40k20-2dqi at40k20-2eqi at40k20-2fqi at40k20-2bgi at40k20-2agi 84j 144q 160q 208q 240q 304q 352g 225g 5v industrial (-40 c to 85 c) usable gates speed grade (ns) ordering code package operation range 20,000-30,000 3 at40k20lv-2ajc at40k20lv-2aqc at40k20lv-2bqc at40k20lv-2cqc at40k20lv-2dqc at40k20lv-2eqc at40k20lv-2fqc at40k20lv-2bgc at40k20lv-2agc 84j 100q 144q 160q 208q 240q 304q 352g 225g 3.3v commercial (0 c to 20 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q 100-lead, very thin (1.0 mm) plastic gull wing quad flat package (vqfp) 144q 144-lead, thin (1.4 mm) plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic gull wing quad flat package (pqfp) 208q 208-lead, plastic gull wing quad flat package (pqfp) 225g 225-lead, ball grid array package (bga) 240q 240-lead, plastic gull wing quad flat package (pqfp) 304q 304-lead, plastic gull wing quad flat package (pqfp) 352g 352-ball, ball grid array package (bga) 432g 432-ball, ball grid array package (bga)
at40k 49 at40k40 ordering information usable gates speed grade (ns) ordering code package operation range 40,000-50,000 2 at40k40-2bqc at40k40-2dqc at40k40-2eqc at40k40-2fqc at40k40-2bgc at40k40-2cgc 144q 208q 240q 304q 352g 432g 5v commercial (0 c to 70 c) 40,000-50,000 2 at40k40-2bqi at40k40-2dqi at40k40-2eqi at40k40-2fqi at40k40-2bgi at40k40-2cgi 144q 208q 240q 304q 352g 432g 5v industrial (-40 c to 85 c) usable gates speed grade (ns) ordering code package operation range 40,000-50,000 3 at40k40lv-3bqc at40k40lv-3dqc at40k40lv-3eqc at40k40lv-3fqc at40k40lv-3bgc at40k40lv-3cgc 144q 208q 240q 304q 352g 432g 3.3v commercial (0 c to 20 c) package type 144q 144-lead, thin (1.4 mm) plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic gull wing quad flat package (pqfp) 208q 208-lead, plastic gull wing quad flat package (pqfp) 225g 225-lead, ball grid array package (bga) 240q 240-lead, plastic gull wing quad flat package (pqfp) 304q 304-lead, plastic gull wing quad flat package (pqfp) 352g 352-ball, ball grid array package (bga) 432g 432-ball, ball grid array package (bga)
at40k 50 packaging information *controlling dimension: millimeters pin 1 id 0.56(0.022) 0.44(0.018) 16.25(0.640) 15.75(0.620) 0.27(0.011) 0.17(0.007) 14.10(0.555) 13.90(0.547) 0.15(0.006) 0.05(0.002) 0.75(0.030) 0.45(0.018) 0-7 0.20(0.008) 0.10(0.004) 1.05(0.041) 0.95(0.037) *controlling dimension: millimeters 1.218(30.95) 1.238(31.45) sq .008(0.20) .016(0.40) pin 1 id .0256(0.65) bsc 1.098(27.90) 1.106(28.10) sq .127(3.22) .157(3.97) .002(0.05) .020(0.50) .025(0.65) .037(0.95) 0 7 .004(0.10) .009(0.23) 84j, 84-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 af 100q, 100-lead, plastic gull wing quad flat package (vqfp) dimensions in millimeters and (inches)* 144q, 144-lead, plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 160q, 160-lead, plastic gull wing quad flat package (pqfp) dimensions in (millimeters) and inches
at40k 51 packaging information *controlling dimension: millimeters *controlling dimension: millimeters *controlling dimension: millimeters pin 1 id 19.90 (0.783) 20.10 (0.791) 0.65 (0.026) bsc 0 7 14.10 (0.555) 13.90 (0.547) 0.36 (0.014) 0.10 (0.004) 2.87 (0.113) 2.57 (0.101) 0.17 (0.007) 0.13 (0.005) 1.03 (0.041) 0.73 (0.029) 1.685 (42.8) 1.669 (42.40) 0.50 (12.7) bsc 0.27 (6.90) 0.17 (4.32) 1.579 (40.11) 1.571 (30.90) 0.40 (0.016) 0.43 (10.92) 0.25 (6.35) 7 0 0.13 (3.30) 0.005 (0.13) 208q, 208-lead, plastic gull wing quad flat package (pqfp) dimensions in (millimeters) and inches 240q, 240-lead, plastic gull wing quad flat package (pqfp) dimensions in (millimeters) and inches 100rq, 100-lead, rectangular plastic gull wing quad flat pack (rqfp) dimensions in millimeters and (inches)* 304q, 304-lead, plastic gull wing quad flat pack (pqfp) dimensions in (millimeters) and inches
at40k 52 packaging information 1.38 (35.1 ) 1.37 (34.9) 0.062 (1.58) max ee dd cc bb aa z y x w v u t r p n m l k j h g f e d c b a 1 (1.25) (1.27) (1.27) 234567891011121314151617 1.25 (31.85) 1.25 (31.65) 1.25 (31.85) 1.25 (31.65) 0.88 (.035) .030 (0.76) 18 19 20 21 22 23 24 25 26 1.38 (35.1) 1.37 (34.9) 1.58 (40.1) 1.53 (39.9) 0.062 (1.58) max kk jj hh gg ff ee dd cc bb aa z y x w v u t r p n m l k j h g f e d c b a 1 (1.25) (1.27) (1.27) 234567891011121314151617 1.50 (38.20) 1.50 (38.00) .035 (0.88) .030 (0.76) 18 19 20 21 22 23 24 25 26 1.50 (38.20) 1.50 (38.00) 27 28 29 30 31 1.58 (40.1) 1.53 (39.9) 352b, 352-ball ball grid array (bga) dimensions in (millimeters) and inches 432b, 432 - ball ball grid array (bga) dimensions in (millimeters) and inches
at40k 53 thermal coefficient table package style lead count theta j-a 0 lfpm theta j-a 225 lfpm theta j-a 500 lpfm theta j-c pqfp 144 33 27 23 8.5 pqfp 160 30 24 20 7 pqfp 208 32 28 24 10 pqfp 240 27 no data no data pqfp 304 19 no data no data tqfp 100 47 39 33 22 rqfp 100 3 plcc 84 37 30 25 12 bga 225 26 no data no data bga 352 bga 432
? atmel corporation 1998. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the companys standard war- ranty which is detailed in atmels terms and conditions located on the companys web site. the company assumes no responsibilit y for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmels pr oducts are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel u.k., ltd. coliseum business centre riverside way camberley, surrey gu15 3yl england tel (44) 1276-686677 fax (44) 1276-686697 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon, hong kong tel (852) 27219778 fax (852) 27221369 japan atmel japan k.k. tonetsu shinkawa bldg., 9f 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4 42 53 60 00 fax (33) 4 42 53 60 01 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 0896bC01/99/xm marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others.

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